ABSTRACT
Circuit complexity and density requirements continue to push PCB fabrication capability limits. Component pitch and routing requirements are continually becoming more aggressive and difficult to achieve in good yield with current fabrication strategies. The trend is to bring the PCB closer to the density requirements currently required for semiconductor packaging. The ability to place interconnecting vias in any location on any layer is crucial to PCB fabricators in meeting this high density interconnect (HDI) trend.

The two fundamental elements in any type of PCB, conductors and dielectrics, both have to be considered when building “any layer” HDI. These PCB’s have specific challenges for processing while maintaining thermal and electrical performance. Careful consideration of the interplay of the fundamental elements is critical to fulfilling all of these requirements.

New methods and materials designed specifically with these challenges in mind are becoming available for building HDI structures without “re-inventing” the PCB shop.

Using materials specifically designed for HDI PCBs can significantly reduce the challenges producing these boards. However, along with easing the challenges of fabrication, these materials must also demonstrate the right combination of properties to meet electrical and thermal requirements while also being reliable. Validation of these new technologies is currently underway.

BACKGROUND
Back in the day, just taking advantage of double-sided-clad increased density. Being able to route traces in the same location on each side of the PCB, interconnected with plated through holes, added significant density compared to a single sided PCB.  Logically, as chips became more powerful with more I/Os, adding layers became the natural progression.

However HDI is not just about layer count. Adding layers has a diminishing return as the through holes and vias grab valuable real estate. Buried vias and “subs” provide an intermediate solution to higher density requirements, but these techniques greatly increase the process complexity and time in the PCB fabrication facility.

As the high density trend marched onward, build-up or sequential lamination became popular as laser drilling and better plating technology enabled blind microvias. Sequential build up has the big density advantage of placing vias anywhere on any layer, but each layer has the process steps of an individual PCB. Lamination and plating capacity must be greatly increased to accommodate this solution.

There is a growing gap between cost-effective PCB manufacturing and HDI PCB requirements. New technologies – materials and methods – are needed for the industry to meet current and future demands.

INTRODUCTION
What if vias could be formed without plating? More importantly, what if the vias could be formed before lamination? If vias could be made this way, trips through plating and lamination can be greatly reduced. Making this possible would require the insertion of a conductor into vias in the dielectric layers between the individual circuit layers.

This can be done several ways. Some methods do this to C-stage (cured) dielectrics and some to B-stage (uncured) dielectrics.

Ideally, the conductive material would be in liquid or paste form so it may be inserted into the vias after drilling, but before lamination. In applying the ink or paste, measures must be taken to ensure that the surface of the dielectric is not contaminated with conductive residue that can lead to electrical leakage, migration, etc.

Creating the interconnecting vias before lamination can greatly simplify the PCB manufacturing while still enabling via placement anywhere on any layer. In addition, formation of conductive vias prior to lamination may be combined with traditional processes for circuit formation and lamination, thus allowing the most efficient and cost-effective use of the PCB shop.

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